Driving circuit

ABSTRACT

A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Patent ApplicationNo. PCT/CN2021/076150 filed on Feb. 9, 2021, which claims priority toChinese Patent Application No. 202010787892.X filed on Aug. 7, 2020. Thedisclosures of these applications are hereby incorporated by referencein their entirety.

BACKGROUND

With the continuous development of mobile devices, battery-poweredmobile devices, such as mobile phones, tablet computers and wearabledevices, are increasingly popular. As an essential element of a mobiledevice, a memory device with a high-speed and low-power storage functionis in great demand.

SUMMARY

The present disclosure relates generally to the field of semiconductordevice technologies, and more specifically to a driving circuit.

One aspect of the present disclosure provides a driving circuit,including:

a primary driving module configured to receive a first signal andgenerate a second signal based on the first signal, driving capabilityof the second signal being greater than that of the first signal; and

an auxiliary driving module connected to an output terminal of theprimary driving module and configured to receive the first signal andgenerate an auxiliary driving signal based on the first signal, theauxiliary driving signal being configured to shorten a rise time of thesecond signal.

Another aspect of the present disclosure provides a driving circuit,including:

a second pull-up transistor configured to generate an auxiliary drivingsignal and output the auxiliary driving signal to a primary drivingmodule, the auxiliary driving signal being configured to shorten a risetime of an output signal of the primary driving module;

a periodic clock generation component configured to generate a clocksignal with a duty ratio of 50%; and

an edge enhancement unit connected to the periodic clock generationcomponent and a control terminal of the second pull-up transistor, theedge enhancement unit being configured to receive the clock signal and afirst signal inputted externally and generate an edge enhancement signalbased on the clock signal and the first signal, and the edge enhancementsignal being configured to control ON/OFF of the second pull-uptransistor.

Details of one or more embodiments of the present disclosure are setforth in the following accompanying drawings and descriptions. Otherfeatures, objectives and advantages of the present disclosure becomeobvious with reference to the specification, the accompanying drawings,and the claims.

BRIEF DESCRIPTION OF DRAWINGS

In order to better describe and illustrate embodiments of the presentdisclosure, reference may be made to one or more accompanying drawings.Additional details or examples used to describe the accompanyingdrawings should not be considered as limitations on the scope of any ofthe invention-creations, the embodiments described hereinafter, and thepreferred embodiments of the present disclosure.

FIG. 1 is a schematic structural diagram of a driving circuit accordingto an embodiment;

FIG. 2 is a schematic structural diagram of a driving circuit accordingto another embodiment;

FIG. 3 is a signal timing diagram according to an embodiment;

FIG. 4 is a diagram showing comparisons of eye pattern test results of asecond signal;

FIG. 5 is a signal timing diagram according to another embodiment;

FIG. 6 is a graph of voltage of the second signal versus time accordingto an embodiment;

FIG. 7 is a schematic structural diagram of a driving circuit accordingto yet another embodiment; and

FIG. 8 is a schematic structural diagram of a duty ratio modulationcircuit according to an embodiment.

DETAILED DESCRIPTION

For easy understanding of the embodiments of the present disclosure, amore comprehensive description of the embodiments of the presentdisclosure will be given below with reference to the relevantaccompanying drawings. Preferred embodiments of the embodiments of thepresent disclosure are given in the drawings. However, the embodimentsof the present disclosure may be implemented in many different forms andis not limited to the embodiments described herein. Rather, theseembodiments are provided to make the contents disclosed in theembodiments of the present disclosure more thorough and comprehensive.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meanings as are commonly understood by those skilled inthe art. The terms used herein in the specification of the embodimentsof the present disclosure are for the purpose of describing specificembodiments only but not intended to limit the embodiments of thepresent disclosure. The term “and/or” used herein includes any and allcombinations of one or more related listed items.

In a memory device, a transmission speed can be increased by driving adata signal through a driving circuit. However, limited by powerconsumption of the memory, driving capability of an existing drivingcircuit may not meet the rapid development of use requirements.

FIG. 1 is a schematic structural diagram of a driving circuit accordingto an embodiment. Referring to FIG. 1, in this embodiment, the drivingcircuit includes a primary driving module 100 and an auxiliary drivingmodule 200.

The primary driving module 100 is configured to receive a first signalDQ and generate a second signal VOH based on the first signal DQ.Driving capability of the second signal VOH is greater than that of thefirst signal DQ. The primary driving module 100 is configured to acquirea data signal from a logic circuit, process the acquired data signal,and transmit a processed signal to a controller through a signalchannel, so as to realize transmission of the data signal. In thisembodiment, the first signal DQ is the data signal acquired from thelogic circuit by the primary driving module 100, and the second signalVOH is the signal processed and sent to the signal channel by theprimary driving module 100. By processing the first signal DQ throughthe primary driving module 100, the driving circuit according to thisembodiment can obtain the second signal VOH with greater drivingcapability, thereby effectively increasing a signal transmission speed.

Illustratively, a memory device can be a dynamic random-access memory(DRAM) or a static random-access memory (SRAM), which may specificallybe, for example, a DRAM, an SRAM, a transistor RAM (TRAM), a zero RAM(Z-RAM), a twin transistor RAM (TTRAM), an MRAM, or the like of a lowpower DDR4 (LPDDR4) or LPDDR4X memory.

The auxiliary driving module 200 is connected to an output terminal ofthe primary driving module 100 and configured to receive the firstsignal DQ and generate an auxiliary driving signal based on the firstsignal DQ. The auxiliary driving signal is configured to shorten a risetime of the second signal VOH.

The various circuits, device components, modules, units, blocks, orportions may have modular configurations, or are composed of discretecomponents, but nonetheless can be referred to as “circuits,”“components,” “modules,” “blocks,” “portions,” or “units” in general. Inother words, the “circuits,” “components,” “modules,” “blocks,”“portions,” or “units” referred to herein may or may not be in modularforms, and these phrases may be interchangeably used.

In some embodiments, the data signal is read and written in response tothe clock signal. Therefore, if a rising edge and/or a falling edge ofthe clock signal arrive/arrives, a to-be-written data signal does notreach a target level, resulting in a data read/write error. For example,if to-be-written data corresponding to an edge time of a current clocksignal is 1 and write data at an edge time of a previous clock signal is0, the second signal VOH is required to be pulled up from a low-levelrange to a high-level range, for example, pulled up from 0.1 V to 1.1 V,between two adjacent edge times of the clock signal, so as to accuratelytransmit the second signal VOH. If the second signal VOH does not reachthe high-level range when the edge time of the current clock signalarrives, the signal transmitted to the signal channel is a low-levelsignal. That is, the actual second signal VOH is not accuratelytransmitted to the signal channel, resulting in a transmission error ofthe second signal VOH.

Further, the memory is further required to achieve faster read/write anddata transmission. For example, an LPDDR is at a data transmission rateof 400 million bits per second (Mbps), an LPDDR2 is at a datatransmission rate of 1600 Mbps, an LPDDR3 is at a data transmission rateof 2133 Mbps, an LPDDR4 is at a data transmission rate of 3200 Mbps, andan LPDDR4X is at a data transmission rate of 4.266 Gbps. Obviously, withthe continuous improvement of the memory, the data transmission rate isalso increasing. In order to realize fast data transmission andread/write, a cycle of a clock signal in the memory is required to bereduced correspondingly. That is, a time interval between two adjacentedges of the clock signal may also be further reduced. If the rise timeof the second signal VOH is too long, a timing margin of the data signalmay be reduced, thereby limiting the transmission and read/write speedsof the memory. Therefore, a speed at which the second signal VOHswitches between the high and low levels is required to be furtherincreased to ensure the correct transmission of the second signal VOH.

In this embodiment, the driving circuit includes: a primary drivingmodule 100 configured to receive a first signal DQ and generate a secondsignal VOH based on the first signal DQ, driving capability of thesecond signal VOH being greater than that of the first signal DQ; and anauxiliary driving module 200 connected to an output terminal of theprimary driving module 100 and configured to receive the first signal DQand generate an auxiliary driving signal based on the first signal DQ,the auxiliary driving signal being configured to shorten the rise timeof the second signal VOH. The driving capability of the first signal DQis improved through the primary driving module 100, and the rise time ofthe second signal VOH is reduced through the cooperation of theauxiliary driving module 200, so that the timing margin of the datasignal is improved, so as to realize faster signal transmission.

FIG. 2 is a schematic structural diagram of a driving circuit accordingto another embodiment. Referring to FIG. 2, in this embodiment, theprimary driving module 100 includes a first pull-up transistor NM1, afirst pull-down transistor MNDN and a pre-driving unit 110.

The first pull-up transistor MN1 and the first pull-down transistor MNDNare configured to generate the second signal VOH together. An outputterminal of the first pull-up transistor MN1 and an output terminal ofthe first pull-down transistor MNDN are connected to each other tooutput the second signal VOH together. The pre-driving unit 110 isconnected to the first pull-up transistor MN1 and the first pull-downtransistor MNDN. The pre-driving unit 110 is configured to receive thefirst signal DQ and control ON/OFF of the first pull-up transistor MN1and ON/OFF of the second pull-up transistor MN2 based on the firstsignal DQ.

Specifically, the first pull-up transistor MN1 is configured to pull avoltage of the second signal VOH up to a first preset level. The firstpreset level falls within the high-level range. The high-level range is,for example, greater than 1 V. The first pull-down transistor MNDN isconfigured to pull the voltage of the second signal VOH down to a secondpreset level. The second preset level falls within the low-level range.The low-level range is, for example, less than 0.2 V. Under the controlof the pre-driving unit 110, the first pull-up transistor MN1 and thefirst pull-down transistor MNDN have different pulling capability. Thetransistor with stronger pulling capability can pull the voltage of thesecond signal VOH to the corresponding first preset level or secondpreset level. For example, if the first pull-up transistor MN1 hasstronger pulling capability, the voltage of the second signal VOH may bepulled up to the first preset level.

The pre-driving unit 110 generates a first control signal and a secondcontrol signal based on the first signal DQ, transmits the first controlsignal to the first pull-up transistor MN1, and transmits the secondcontrol signal to the first pull-down transistor MNDN.

In some examples, the first pull-up transistor MN1 and the firstpull-down transistor MNDN may be of the same type. Transistor typesinclude an N type and a P type. When the first pull-up transistor MN1and the first pull-down transistor MNDN are of the same type, the firstpull-up transistor MN1 and the first pull-down transistor MNDN are bothturned on at a high level or both turned on at a low level. Therefore,the first pull-up transistor MN1 and the first pull-down transistor MNDNcan be controlled by enabling the first control signal and the secondcontrol signal to be in opposite level states, for example, enabling thefirst control signal to be at a high level and the second control signalto be at a low level, so that the two transistors have different pullingcapability. Further, the pre-driving unit 110 may be provided with aninverter with an input terminal connected to the first control signal,so as to invert the first control signal to generate the second controlsignal.

In some other examples, the first pull-up transistor MN1 and the firstpull-down transistor MNDN may also be of different types. When the firstpull-up transistor MN1 and the first pull-down transistor MNDN are ofdifferent types, one of the first pull-up transistor MN1 and the firstpull-down transistor MNDN is turned on at a high level, and the other isturned on at a low level. Therefore, the first pull-up transistor MN1and the first pull-down transistor MNDN can be controlled by enablingthe first control signal and the second control signal to be in the samelevel state, for example, enabling the first control signal and thesecond control signal to be at a high level, so that the two transistorshave different pulling capability, and a control signal generationcircuit can be simplified.

In one embodiment, still referring to FIG. 2, the first pull-uptransistor MN1 and the first pull-down transistor MNDN are both N-typetransistors. Specifically, power consumption is an important referencefactor during the design of the driving circuit, and can be estimatedwith reference to the following formula:

P _(out)=½C _(Load) ×V _(DD) ×V _(swing)

where C_(Load) denotes load capacitance, V_(DD) denotes a power supplyvoltage VDDQL,V_(swing) denotes an output voltage swing, and P_(out)denotes output power. According to the formula, the output power can bereduced when any one of the load capacitance, the power supply voltageVDDQL and the output voltage swing is reduced. In this embodiment, anN-type transistor is used as the first pull-up transistor MN1. TheN-type transistor has better load capacitance characteristics than theP-type transistor due to its own structural characteristics. Therefore,the output power consumption of the driving circuit can be effectivelyreduced by using the N-type transistor.

Compared with the P-type first pull-up transistor MN1, the N-type firstpull-up transistor MN1 can transmit a signal at a voltage lower than thepower supply voltage VDDQL. Therefore, compared to the driving circuitin which the first pull-up transistor MN1 is a P-type transistor, thedriving circuit according to this embodiment can transmit a signal witha smaller output voltage swing than the driving circuit in which thefirst pull-up transistor MN1 is a P-type transistor. For example, theLPDDR4X has an output voltage swing of 0.366 V, and the LPDDR4 has anoutput voltage swing of 0.3 V. Therefore, the LPDDR4X using the N-typefirst pull-up transistor MN1 can reduce the power consumption by about20% compared to the LPDDR4. In addition, compared to the P-typetransistor, a size of the primary driving module 100 can be effectivelyreduced by using the N-type transistor as the first pull-up transistorMN1. Furthermore, symmetry characteristics of the first pull-uptransistor MN1 and the first pull-down transistor MNDN can be improvedby enabling the first pull-up transistor MN1 and the first pull-downtransistor MNDN to be the same N-type transistor, so as to furtherimprove the performance of the driving circuit.

In one embodiment, a drain of the first pull-up transistor MN1 isconnected to the power supply voltage VDDQL, a source of the firstpull-up transistor MN1 is connected to a drain of the first pull-downtransistor MNDN, and a source of the first pull-down transistor MNDN isconnected to a ground voltage GND. The source of the first pull-uptransistor MN1 and the drain of the first pull-down transistor MNDN areconfigured to output the second signal VOH together.

Specifically, in this embodiment, the first preset level is the powersupply voltage VDDQL, and the second preset level is the ground voltageGND. When the first control signal is at a high level and the secondcontrol signal is at a low level, the first pull-up transistor MN1 isturned on, the first pull-down transistor MNDN is turned off, and thesecond signal VOH is pulled up to the power supply voltage VDDQL. Whenthe first control signal is at a low level and the second control signalis at a low level, the first pull-up transistor MN1 is turned off, thefirst pull-down transistor MNDN is turned on, and the second signal VOHis pulled down to the ground voltage GND. Further, through thecooperation of the auxiliary driving module 200, this embodiment canreduce the rise time when the second signal VOH switches from a lowlevel to a high level, so as to enlarge a signal timing margin toprovide a more reliable and faster output signal.

In one embodiment, still referring to FIG. 2, the auxiliary drivingmodule 200 includes a second pull-up transistor MN2 and an edgeenhancement unit 210.

The second pull-up transistor MN2 is configured to generate theauxiliary driving signal. The auxiliary driving signal may be, forexample, a charging current. That is, the auxiliary driving module 200is configured to generate a charging current based on the first signalDQ. The charging current is configured to speed up the charging of thesecond signal VOH to reduce the rise time of the second signal VOH. Whenthe second signal VOH is required to switch from a low level to a highlevel, the auxiliary driving module 200 is required to be turned on;that is, the second pull-up transistor MN2 is controlled to be turned onby the edge enhancement unit 210, so that the second pull-up transistorMN2 outputs the charging current to the primary driving module 100. Thecharging current can speed up the charging of the output terminal of theprimary driving module 100, thereby reducing the rise time of the secondsignal VOH.

Specifically, the second pull-up transistor MN2 is an N-type transistor,a control terminal of the second pull-up transistor MN2 is connected tothe edge enhancement unit 210, a drain of the second pull-up transistorMN2 is connected to the power supply voltage VDDQL, and a source of thesecond pull-up transistor MN2 is configured to output the auxiliarydriving signal. That is, both the second pull-up transistor MN2 and thefirst pull-up transistor MN1 are connected to the power supply voltageVDDQL. Therefore, when the second pull-up transistor MN2 is turned on, avoltage of the output terminal of the primary driving module 100 mayrise rapidly to a high level, thereby reducing the rise time of thesecond signal VOH. Similar to the first pull-up transistor MN1, theN-type second pull-up transistor MN2 can transmit a signal at a voltagelower than the power supply voltage VDDQL. The driving circuit accordingto this embodiment can transmit a signal with a smaller output voltageswing than the driving circuit in which the second pull-up transistorMN2 is a P-type transistor. For example, the LPDDR4X has an outputvoltage swing of 0.366 V, and the LPDDR4 has an output voltage swing of0.3 V. Therefore, the LPDDR4X can reduce the power consumption by about20% compared to the LPDDR4. In addition, compared to the P-typetransistor, a size of the auxiliary driving module 200 can beeffectively reduced by using the N-type transistor as the second pull-uptransistor MN2.

The edge enhancement unit 210 is connected to a control terminal of thesecond pull-up transistor MN2 and configured to receive the first signalDQ and generate an edge enhancement signal based on the first signal DQ.The edge enhancement signal is configured to control ON/OFF of thesecond pull-up transistor MN2. The edge enhancement signal acts as anenable signal to control the second pull-up transistor MN2. The edgeenhancement signal includes a high level and a low level. That is, whenthe signal is in a high-level stage, the second pull-up transistor MN2is controlled to be turned on to output the auxiliary driving signal, soas to speed up the switching of the second signal VOH from a low levelto a high level. When the signal is in a low-level stage, the secondpull-up transistor MN2 is controlled to be turned off and does notoutput the auxiliary driving signal.

In one embodiment, the edge enhancement unit 210 includes a pulsegeneration component 211, a periodic clock generation component 212 andan arithmetic component 213.

Specifically, the pulse generation component 211 is configured toreceive the first signal DQ and generate a pulse signal based on thefirst signal DQ. The periodic clock generation component 212 isconfigured to generate a clock signal. The arithmetic component 213 isconnected to the pulse generation component 211 and the periodic clockgeneration component 212. The arithmetic component 213 is configured togenerate the edge enhancement signal based on the pulse signal and theclock signal. The clock signal may also come from outside the edgeenhancement unit 210. The periodic clock generation component 212 can beinactive or only plays a delaying role. FIG. 3 is a signal timingdiagram according to an embodiment. Referring to FIG. 3, a cycle of theclock signal is matched with a cycle of data update of the first signalDQ, so as to ensure the accuracy of signal read/write timing.

Further, the pulse generation component 211 responds to a rising edge ofthe first signal DQ and generates the pulse signal. The clock signal isconfigured with a preset clock cycle, and a width of a high level of thepulse signal is less than or equal to half of the clock cycle. Forexample, as shown in FIG. 3, the width of the high level of the pulsesignal is equal to a width of a high level of the clock signal. It maybe understood that the influence of the pulse signal maintained at ahigh level on the power consumption of the driving circuit is higherthan that of the pulse signal maintained at a low level on the powerconsumption of the driving circuit. Therefore, on the premise ofensuring accurate signal transmission, better power performance can beachieved by narrowing the width of the high level of the pulse signal.Specifically, an appropriate width of the high level can be selectedaccording to a signal timing margin and a power consumption requirement.For example, the width of the high level of the pulse signal may be ⅓,¼, etc. of the clock cycle. Further, the second signal VOH cannot beaccurately driven based on the pulse signal when the width of the highlevel of the pulse signal generated by the pulse generation component211 is greater than half of the clock cycle. It may be understood thatthe periodic clock generation component 212 has better stability thanthe pulse generation component 211. Therefore, the operation unit 213can choose to output a clock signal to ensure the accurate signaldriving when the high level width of the pulse signal does not meet therequirement.

FIG. 4 is a diagram showing comparisons of eye pattern test results of asecond signal VOH. Referring to FIG. 4, two test patterns on the leftare test results of the second signal VOH in a case where a comparisondriving circuit is used. Due to the insufficient rising speed of thesecond signal VOH at the position pointed by the arrow in the upper lefttest pattern, the rise time of the second signal VOH is too long,thereby leading to serious noise. That is, the lower left eye patterntest results are not open enough, and the signal timing margin is low.Two test patterns on the right are test results of the second signal VOHin a case where the driving circuit according to this embodiment isused. Due to the obviously increased rising speed of the second signalVOH at the position pointed by the arrow in the upper right testpattern, noise in the lower right eye pattern test results is reducedand the signal timing margin is increased.

In one embodiment, a width of a high level of the edge enhancementsignal is less than or equal to a width of a high level of the pulsesignal. Still referring to FIG. 3, in the embodiment shown in FIG. 3,the width T2 of the high level of the edge enhancement signal is lessthan the width of the high level T1 of the pulse signal. A rising edgeof the edge enhancement signal is delayed for a time T3 compared to arising edge of the pulse signal, and a falling edge of the edgeenhancement signal is substantially aligned with a falling edge of thepulse signal (there may be several logic-gate delays in a real circuit).

FIG. 5 is a signal timing diagram according to another embodiment. Thewidth T2 of the high level of the edge enhancement signal in theembodiment shown in FIG. 5 is wider than the width T2 of the high levelof the edge enhancement signal shown in FIG. 3; that is, the delay timeT3 is adjustable. The arithmetic component 213 may include amultiplexer. The multiplexer is connected to the pulse generationcomponent 211 and the periodic clock generation component 212, and themultiplexer chooses to output the pulse signal, so that the width of thehigh level of the edge enhancement signal can be equal to or less thanthe width of the high level of the pulse signal. At the same time, therising edge of the edge enhancement signal can be controlled to delayfor a certain time, for example, the delay time T3 in FIG. 3 and FIG. 5,compared to the rising edge of the pulse signal, and a falling edge ofthe edge enhancement signal can also be controlled to be substantiallyaligned with a falling edge of the pulse signal.

Referring to FIG. 2, FIG. 3 and FIG. 4 together, the edge enhancementsignal is generated only when the second signal VOH is close to a highvoltage threshold stage. Limited by the NMOS transistor drivingstructure used in FIG. 2, a pull-up effect of the MN1 transistor on thesecond signal VOH becomes weak when the second signal VOH rises close tothe high voltage threshold stage, resulting in a slow rising speed ofthe second signal VOH at the high voltage threshold stage. In this case,the edge enhancement signal causes the MN2 transistor to be turned on,and the MN1 transistor and the MN2 transistor pull up the second signalVOH together, which can accelerate the rising of the second signal VOH.In fact, the pull-up effect of the MN1 transistor on the second signalVOH becomes weaker and weaker as the second signal VOH rises. If theedge enhancement signal causes the MN2 transistor to be turned onearlier, the second signal VOH can rise faster beyond the high voltagethreshold, but this also consumes more power. Therefore, the risingspeed of the second signal VOH and the power consumption should beconsidered when a pulse rising edge of the edge enhancement signalgenerated by the edge enhancement unit arrives.

In one embodiment, the edge enhancement signal includes a plurality ofenhanced pulses, the pulse signal includes a plurality of initialpulses, the enhanced pulses are in one-to-one correspondence to theinitial pulses, and a falling edge of the enhanced pulse is aligned witha falling edge of the corresponding initial pulse. Specifically, in theembodiment shown in FIG. 3, the edge enhancement signal includes threeenhanced pulses, the pulse signal includes three initial pulses, and thefirst enhanced pulse corresponds to the first initial pulse, the secondenhanced pulse corresponds to the second initial pulse, and the thirdenhanced pulse corresponds to the third initial pulse. The timingaccuracy of the edge enhancement signal can be improved by aligning thefalling edge of the enhanced pulse with the falling edge of thecorresponding initial pulse.

In one embodiment, a rising edge of the enhanced pulse is delayed for apreset time period compared to a rising edge of the correspondinginitial pulse. The preset time period is the time T3 shown in theembodiment of FIG. 3. In this embodiment, the generation time of theauxiliary driving signal can be controlled by delaying the edgeenhancement signal, so that the timing of the auxiliary driving signalis matched with that of the second signal VOH, so as to achieve a betterdriving effect.

FIG. 6 is a graph of voltage of the second signal VOH versus timeaccording to an embodiment. FIG. 6 shows voltage changes during theswitching of the second signal VOH from a low level to a high level. Thesolid line in FIG. 6 shows a curve of the second signal VOH outputtedfrom comparison driving circuit, and the dashed line in FIG. 6 shows acurve of the second signal VOH outputted from the driving circuitaccording to this embodiment. Referring to FIG. 6, at an early stage ofthe switching of the second signal VOH from the low level to the highlevel, the voltage rises faster, and the rising of the voltage graduallyslows down with the constant increase in the voltage of the secondsignal VOH. It may be understood that, if the auxiliary driving signalis outputted in a time period when the voltage of the second signal VOHrises faster, it has little improvement effect on the rising speed ofthe voltage of the second signal VOH. Therefore, this embodiment canmake the auxiliary driving signal arrive at the output terminal of thesecond signal VOH at an appropriate time, so as to achieve a bettereffect of improving the rise time of the second signal VOH with lowerenergy consumption.

Further, in an example where the auxiliary driving signal is a chargingcurrent, a generation time of the charging current is equal to or laterthan a first time. The first time may be, for example, a time at which avoltage of the second signal VOH rises to a low level threshold. Thefirst time is the time t1 in FIG. 6. Power consumption of the drivingcircuit can be reduced by making the generation time of the chargingcurrent equal to or later than the first time. Furthermore, thegeneration time of the charging current may be, for example, a time t2,a time t3, or the like. An appropriate generation time can bespecifically selected according to the driving capability of the firstpull-up transistor MN1 and the first pull-down transistor MNDN. FIG. 6illustrates that an auxiliary charging current is generated from thetime t3.

FIG. 7 is a schematic structural diagram of a driving circuit accordingto yet another embodiment. Referring to FIG. 7, in this embodiment, thedriving circuit includes a second pull-up transistor MN2, a periodicclock generation component 212 and an edge enhancement unit 210.

The second pull-up transistor MN2 is configured to generate an auxiliarydriving signal and output the auxiliary driving signal to a primarydriving module 100. The auxiliary driving signal is configured toshorten the rise time of an output signal of the primary driving module100. The periodic clock generation component 212 is configured togenerate a clock signal with a duty ratio of 50%. The edge enhancementunit 210 is connected to the periodic clock generation component 212 anda control terminal of the second pull-up transistor MN2. The edgeenhancement unit 210 is configured to receive the clock signal and afirst signal DQ inputted externally and generate an edge enhancementsignal based on the clock signal and the first signal DQ. The edgeenhancement signal is configured to control ON/OFF of the second pull-uptransistor. It may be understood that in a DDR memory, both rising andfalling edges of the clock signal are required to be configured for dataread and write and transmission. However, changes in a manufacturingprocess, a temperature and other parameters may lead to a decrease inthe duty ratio of the clock signal, thereby resulting in signal jitter.Therefore, the corresponding signal jitter can be avoided by making theduty ratio of the clock signal 50%, so as to improve the reliability ofthe clock signal.

In one embodiment, the periodic clock generation component 212 includesa clock signal generation circuit 2121 and a duty ratio modulationcircuit 2122. The clock signal generation circuit 2121 is configured togenerate a clock signal configured with a preset clock cycle. The dutyratio modulation circuit 2122 is connected to the clock signalgeneration circuit 2121 and configured to modulate the clock signal sothat the duty ratio of the clock signal is 50%.

Further, FIG. 8 is a schematic structural diagram of a duty ratiomodulation circuit 2122 according to an embodiment. Referring to FIG. 8,in this embodiment, the duty ratio modulation circuit 2122 includes aphase converter 2123 and a cross-coupled latch 2124. The phase converter2123 is connected to the clock signal generation circuit 2121 andconfigured to receive the clock signal and convert a phase of the clocksignal to generate a converted signal. A phase difference between theconverted signal and the clock signal is 180°. The cross-coupled latch2124 is connected to the phase converter 2123 and configured to receivethe clock signal and the converted signal and modulate the duty ratiobased on the clock signal and the converted signal so that the dutyratio of the clock signal is 50%. Illustratively, the cross-coupledlatch 2124 includes two anti-parallel inverters. In this embodiment,through the cooperation between the phase converter 2123 and thecross-coupled latch 2124, the duty ratio of the clock signal can bemodulated with a simpler circuit structure, so that the jitter of theclock signal can be improved, thereby obtaining a wider timing margin.

Technical features of the above embodiments may be combined in variousways. To make descriptions brief, not all possible combinations of thetechnical features in the embodiments are described. Therefore, as longas there is no contradiction between the combinations of the technicalfeatures, they should all be considered as scopes disclosed in thespecification.

The above embodiments merely describe several implementations of theembodiments of the present disclosure, and their description is specificand detailed, but cannot therefore be understood as a limitation on thepatent scope of the present disclosure. It should be noted that those ofordinary skill in the art may further make variations and improvementswithout departing from the conception of the embodiments of the presentdisclosure, and these all fall within the protection scope of theembodiments of the present disclosure. Therefore, the patent protectionscope of the embodiments of the present disclosure should be subject tothe appended claims.

What is claimed is:
 1. A driving circuit, comprising: a primary drivingmodule configured to receive a first signal and generate a second signalbased on the first signal, driving capability of the second signal beinggreater than that of the first signal; and an auxiliary driving moduleconnected to an output terminal of the primary driving module andconfigured to receive the first signal and generate an auxiliary drivingsignal based on the first signal, the auxiliary driving signal beingconfigured to shorten a rise time of the second signal.
 2. The drivingcircuit according to claim 1, wherein the primary driving modulecomprises: a first pull-up transistor; a first pull-down transistor; anda pre-driving unit connected to the first pull-up transistor and thefirst pull-down transistor, the pre-driving unit being configured toreceive the first signal and control ON/OFF of the first pull-uptransistor and ON/OFF of the second pull-up transistor based on thefirst signal; wherein the first pull-up transistor and the firstpull-down transistor are configured to generate the second signaltogether, and an output terminal of the first pull-up transistor and anoutput terminal of the first pull-down transistor are connected to eachother to output the second signal together.
 3. The driving circuitaccording to claim 2, wherein the first pull-up transistor and the firstpull-down transistor are both N-type transistors.
 4. The driving circuitaccording to claim 3, wherein a drain of the first pull-up transistor isconnected to a power supply voltage, a source of the first pull-uptransistor is connected to a drain of the first pull-down transistor,and a source of the first pull-down transistor is connected to a groundvoltage; wherein the source of the first pull-up transistor and thedrain of the first pull-down transistor are configured to output thesecond signal together.
 5. The driving circuit according to claim 1,wherein the auxiliary driving module comprises: a second pull-uptransistor configured to generate the auxiliary driving signal; and anedge enhancement unit connected to a control terminal of the secondpull-up transistor and configured to receive the first signal andgenerate an edge enhancement signal based on the first signal, the edgeenhancement signal being configured to control ON/OFF of the secondpull-up transistor.
 6. The driving circuit according to claim 5, whereinthe second pull-up transistor is an N-type transistor.
 7. The drivingcircuit according to claim 6, wherein the control terminal of the secondpull-up transistor is connected to the edge enhancement unit, a drain ofthe second pull-up transistor is connected to a power supply voltage,and a source of the second pull-up transistor is configured to outputthe auxiliary driving signal.
 8. The driving circuit according to claim5, wherein the edge enhancement unit comprises: a pulse generationcomponent configured to receive the first signal and generate a pulsesignal based on the first signal; a periodic clock generation componentconfigured to generate a clock signal; and an arithmetic componentconnected to the pulse generation component and the periodic clockgeneration component, the arithmetic component being configured togenerate the edge enhancement signal based on the pulse signal and theclock signal.
 9. The driving circuit according to claim 8, wherein thepulse generation component responds to a rising edge of the first signaland generates the pulse signal; wherein the clock signal is configuredwith a preset clock cycle, and a width of a high level of the pulsesignal is less than or equal to half of the clock cycle.
 10. The drivingcircuit according to claim 8, wherein a width of a high level of theedge enhancement signal is less than or equal to a width of a high levelof the pulse signal.
 11. The driving circuit according to claim 8,wherein the edge enhancement signal comprises a plurality of enhancedpulses, the pulse signal comprises a plurality of initial pulses, theenhanced pulses are in one-to-one correspondence to the initial pulses,and a rising edge of the enhanced pulse is delayed for a preset timeperiod compared to a rising edge of the corresponding initial pulse. 12.The driving circuit according to claim 8, wherein the edge enhancementsignal comprises a plurality of enhanced pulses, the pulse signalcomprises a plurality of initial pulses, the enhanced pulses are inone-to-one correspondence to the initial pulses, and a falling edge ofthe enhanced pulse is aligned with a falling edge of the correspondinginitial pulse.
 13. The driving circuit according to claim 1, wherein theauxiliary driving module is configured to generate a charging currentbased on the first signal, the charging current being configured toaccelerate a charging speed of the second signal to reduce the rise timeof the second signal.
 14. The driving circuit according to claim 13,wherein a generation time of the charging current is equal to or laterthan a first time; wherein the first time is a time at which a voltageof the second signal rises to a low level threshold.
 15. A drivingcircuit, comprising: a second pull-up transistor configured to generatean auxiliary driving signal and output the auxiliary driving signal to aprimary driving module, the auxiliary driving signal being configured toshorten a rise time of an output signal of the primary driving module; aperiodic clock generation component configured to generate a clocksignal with a duty ratio of 50%; and an edge enhancement unit connectedto the periodic clock generation component and a control terminal of thesecond pull-up transistor, the edge enhancement unit being configured toreceive the clock signal and a first signal inputted externally andgenerate an edge enhancement signal based on the clock signal and thefirst signal, and the edge enhancement signal being configured tocontrol ON/OFF of the second pull-up transistor.
 16. The driving circuitaccording to claim 15, wherein the periodic clock generation componentcomprises: a clock signal generation circuit configured to generate aclock signal configured with a preset clock cycle; and a duty ratiomodulation circuit connected to the clock signal generation circuit andconfigured to modulate the clock signal so that the duty ratio of theclock signal is 50%.
 17. The driving circuit according to claim 15,wherein the duty ratio modulation circuit comprises: a phase converterconnected to the clock signal generation circuit and configured toreceive the clock signal and convert a phase of the clock signal togenerate a converted signal, a phase difference between the convertedsignal and the clock signal being 180°; and a cross-coupled latchconnected to the phase converter and configured to receive the clocksignal and the converted signal and modulate the duty ratio based on theclock signal and the converted signal so that the duty ratio of theclock signal is 50%.